1. Field of the Invention
The present invention relates in general to memories having spare rows and columns of memory cells that can be used to replace rows and columns having defective cells, and in particular to an apparatus for testing such a memory and generating data for facilitating allocation of spare rows and columns.
2. Description of Related Art
A typical random access memory (RAM) includes an array of rows and columns of memory cells, each cell having a unique combination of row and column address. Many RAMs include redundant storage elements in the form of spare rows and columns of memory cells. When such a RAM is found to have a defective memory cell, a row or column containing that memory cell can be replaced with one of the RAM's spare rows or columns. The replacement is accomplished by using a laser or other means to alter the RAM so that the spare row or column is addressed in lieu of the row or column containing the defective cell.
When such a RAM has a defective cell it can be repaired by replacing either its row or column with a spare row or column. However it is important to allocate spare rows and columns efficiently. For example assume a RAM has one spare row and three spare columns. Assume also that the RAM has 6 defective cells with three of them occurring in its first row. If we replace the first row with the spare row, then we can use the three spare columns to replace columns containing the three defective cells that are not in the first row. However if we use the three spare columns to replace the columns containing the three cells in the first row, we may not have enough remaining spare rows and columns to replace the three cells that are not in the first row.
Prior art memory testers typically test each memory cell of a RAM device under test (DUT) by writing data to the memory cell and then reading the data back out to determine whether the data read out matches the data written into the cell. A high speed memory tester employs a pattern generator or counters to produce the data, address and control signals needed to write data into the memory cells and read it back out. A hardware comparator typically compares the memory input and output data and supplies data indicating the result of the comparison to an "error capture memory" having one storage memory for each memory cell to store the results of the comparison. After each memory cell of the DUT has been tested, the contents of the error capture memory constitutes a bit map of the DUT, with each bit indicating whether a corresponding memory cell of the DUT is defective. Following the test, a host computer reads the contents of the error capture memory and determines therefrom how best to allocate spare rows and columns when replacing the defective memory cells.
One problem with this system is that since the error capture memory has to have as many cells as the memory being tested, and since memories can be quite large, it takes a relatively long time for the host computer to read all of the data out of the error capture memory. In a production environment where thousands of memories are being tested in succession, the total time the host computer requires to read the captured error data is substantial and comprises a significant portion of the time required to test the memories.
Thus it would be beneficial to provide a memory test system that can quickly test a memory and quickly provide a host computer with a relatively small amount of data that will enable the host computer to determine how to allocate spare rows and columns, and which does not require the host computer to read the entire contents of an error capture memory.